The cost and complexity associated with scaling of semiconductor device sizes according to Moore's law has given rise to new methods to improve semiconductor device characteristics. New gate materials such as high-k gate dielectrics and metal gates to decrease device leakage, FinFET devices with increased effective gate area as compared to same-size planar devices, and strain inducing channels for increased charge carrier mobility are a few examples of methods to continue Moore's Law scaling for next generation microprocessor designs.